System-on-Chip engineering, S.L. (SoC-e)
•
HQ:
Spain
HSR-PRP Switch (HPS) is an IP Core for the implementation of High-availability Seamless Redundancy and Parallel Redundancy Protoc…
- Ethernet
Compare 18 System-on-Chip engineering, S.L. (SoC-e) IP Cores from 1 vendors
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IEEE 1588 V2 CPU-less Slave Clock
System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain1588Tiny is a IEEE1588-2008 V2 Slave Only hard-only compliant clock synchronization IP core for Xilinx FPGAs.
- IEEE-1588 / PTP
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES).
- Ethernet
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
Deterministic Ethernet solutions, like TSN, deliver streams with guaranteed bandwidth and deterministic latency.
- Ethernet
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100M/1G/2.5G/5G/10G Managed Ethernet Switch
System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain10G Managed Ethernet Switch (MES) IP core features a full-speed, Head-Of-Line effect free crossbar matrix that allows continuous …
- Ethernet
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AVB/Automotive Ethernet Switch
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainThe demand for higher bandwidth in the car is growing quickly.
- Ethernet
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IEC 61850/62351 Substation Automation Systems Cryptographic IP Core
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainIEC 61850/62351 Substation Automation Systems Cryptographic (SASCrypt) IP Core secures the strict real-time traffic used in the S…
- Symmetric Crypto
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
Time Sensitive Networking (TSN) is the name of the IEEE 802.1 Task Group responsible for standards at Data Link Layer.
- Ethernet
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Time Synchronization Redundancy
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainMULTIsync IP Core is a multi-protocol redundant time synchronization core that provides sub-microsecond time synchronization, pro…
- IEEE-1588 / PTP
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
IRIGtimeS implements an IRIG 200-04 compliant time synchronization slave on FPGA devices.
- IEEE-1588 / PTP
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices.
- IEEE-1588 / PTP
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IEEE 1588 V2 Ordinary and Boundary Clock
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainPreciseTimeBasic is a IEEE1588-2008 V2 compliant clock synchronization IP core for Xilinx FPGAs.
- IEEE-1588 / PTP
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Configuration-over-Ethernet (COE) IP Core
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainConfiguration-over-Ethernet (COE) is a Layer 2 configuration protocol design by SoC-e to access remotely to FPGAs that implements…
- Ethernet
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
ManagedRedundantSwitch IP core (MRS) is a combination of SoCe HSR-PRPSwitch (HPS) and ManagedEthernetSwitch (MES) IP cores offeri…
- Ethernet
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Time Sensitive Networking Switch
System-on-Chip engineering, S.L. (SoC-e)• HQ: SpainIndustrial Internet of Things (IIoT) offers smart infrastructure and hyper-connected devices with sensing, processing and network…
- Ethernet
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
Unmanaged Ethernet Switch IP core (UES) implements a plug-and-play Ethernet switch on reconfi gurable devices.
- Ethernet
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
Managed Ethernet Switch (MES) IP core features a non-blocking crossbar matrix that allows continuous transfers between all the po…
- Ethernet
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System-on-Chip engineering, S.L. (SoC-e)• HQ: Spain
The SoC-e PROFINET Switch IP core is an Intellectual Property (IP) Core for FPGAs.
- Ethernet