The Stream Buffer Controller IP Core is optimized for Intel (Altera) and Xilinx FPGAs and implements a versatile Stream to Memory…
- System Controller
- IN BETA PHASE
The Stream Buffer Controller IP Core is optimized for Intel (Altera) and Xilinx FPGAs and implements a versatile Stream to Memory…
The Stream Buffer Controller IP Core implements a versatile Stream to Memory Mapped DMA bridge with 16 independent streams.
The Display Controller IP Core enables the easy addition of a display to existing or future FPGA designs, allowing the system des…
The Enclustra Universal Drive Controller IP Core enables the easy addition of drive control capabilities to existing or future FP…
Enclustra's UDP/IP Ethernet IP core easily enables FPGA-based subsystems to communicate with other subsystems via Ethernet, using…