UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant
This macro-cell is an ultra low power analog/RF front-end core designed for SilTerra 0.18μm CMOS technology.
Overview
This macro-cell is an ultra low power analog/RF front-end core designed for SilTerra 0.18μm CMOS technology. It is ideal for use in passive UHF RFID integrated circuits compliant with EPCGlobal Class 1 Gen 2 / ISO18000-6C standards.
The circuit features a complete analog/RF front-end including rectifier, demodulator, backscattering modulator, a power management unit (PMU) and a short-term memory (STM) that generates the persistence flags. The PMU includes an output supply voltage limiter, internal voltage and current references, built-in power-on-reset (POR), and oscillator. Internal blocks are trimmable via a digital word that can reside in the non-volatile memory of the chip.
Key features
- −12dBm read sensitivity
- Output supply voltage from 1V to 1.8V
- Internal 1.12V voltage reference
- Internal 15.5nA current bias
- Internal 2MHz oscillator
- Built-in POR
- Persistence flags generator
- Current consumption: 1.5µA
Block Diagram
Applications
- Passive/Active EPCGlobal C1G2 / ISO18000-6C RFID tag ICs
What’s Included?
- Datasheet/Integration Guide
- HDLModel
- Flat GDSII database/LVS netlist
- Customer Support
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about RF Front End IP cores
What is UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant?
UHF Passive RFID Front-End - EPCGlobal Class 1 Gen 2/ISO18000-6C Compliant is a RF Front End IP core from Chipus Microelectronics listed on Semi IP Hub.
How should engineers evaluate this RF Front End?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RF Front End IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.