Overview
The UFS 2.1 Host Stack is a stack developed for UFS Host Controllers that are used to connect to UFS devices via UniPro/M-PHY. The stack can also be used for validating a UFS device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
The modular UFS 2.1 Host Stack is architected to be OS and platform independent which eases porting effort. It has thin OS and hardware abstraction layers making it highly portable.
The UFS 2.1 Host Stack has a low-level hardware layer that is purely OS independent and users can use this layer alone for UFS host/device validation with no driver complexity. The UFS stack provides a generic API set to access, control, and configure the bus driver, host controller driver, and the underlying hardware. The stack includes functions for UFS initialization, UniPro attributes configuration, sending/Receiving of commands/tasks in the form of UPIUs, data transfer, UFS interrupt handling, UFS device configuration, and UFS host controller hardware configuration. The UFS 2.1 Host Stack can support a single UFS host controller with a single UFS Device.
The UFS host stack consists of the following layers:
- a) Application Interface Layer (API Layer)
- b) Protocol Layer
- c) Host Controller Driver Layer
- d) Low level Hardware Abstraction Layer
- e) OS Abstraction Layer
The layered architecture allows for easy porting to various operating systems and various platforms. Client applications such as the function drivers interface with the API layer to use the UFS device. The low level details of the protocol is abstracted for the end-user and is handled in the software stack. A set of well defined APIs are provided at this layer.
Learn more about UFS Controller IP core
In the world of mobile and embedded electronics, storage is no longer just about capacity; it’s about how fast that data can move. As we transition into an era of on-device AI and 8K video, the standards we rely on—UFS, eMMC, and NAND—are evolving rapidly.
UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.
Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.
The emerging MIPI standards are designed to ensure interoperability among devices and software that are used in products for the exploding hand-held market. The standards facilitate the interconnection of multiple, mixed-signal integrated circuit devices on a single hand-held product. Use of the standards ensures low power, low pin count and interoperability of all the devices in the system and easy integration.
As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors Ltd. for the development of a generic Virtual Platform using TLM 2.0; reusable for any system model.
With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.
