Vendor: SmartDV Technologies Category: Test / Debug

SWD Verification IP

SWD(Serial Wire Debug) Verification IP provides an efficient and simple way to debug and trace functionality on processor cores a…

Verification IP View all specifications

Overview

SWD(Serial Wire Debug) Verification IP provides an efficient and simple way to debug and trace functionality on processor cores and System on Chip (SoC) devices. The SmartDV's SWD Verification IP is fully compliant with ARM Serial Wire Debug interface Specification and provides the following features.

SWD Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SWD Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports ARM Serial Wire Debug Interface specifications.
  • Full SWD Host and Device functionality.
  • Supports single bidirectional data connection and a separate clock to transfer data synchronously.
  • Supports START and STOP bit generation and handling.
  • Supports DP or AP register accessing.
  • Supports WAIT response to read or write operation request.
  • Supports FAULT response to read or write operation request.
  • Supports Line reset.
  • Supports Header and Data parity generation.
  • Supports Header and Data parity error checks.
  • Supports Sticky overrun behavior.
  • Supports SW-DP write buffering.
  • Supports insertion of errors on below
    • Stop bit
    • Park bit
    • Random Write NACK insertion by Device
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Callbacks in Host and Device for various events.
  • Functional coverage of complete SWD specs.
  • SWD Verification IP comes with complete testsuite to test every feature of SWD specification.

Block Diagram

Benefits

  • Faster testbench development and more complete verification of SWD designs.
  • Easy to use command interface simplifies testbench control and configuration of Host and Device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the SWD testcases to certify SWD Host/Device device.
  • Examples showing how to connect various components, and usage of Host, Device and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
SWD VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

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Frequently asked questions about SerDes Test / Debug IP cores

What is SWD Verification IP?

SWD Verification IP is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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