Vendor: Obsidian Technology Category: Test / Debug

JTAG 2-Wire to 4-Wire Adapter

The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port.

Overview

The OT4001_cjtag is an adapter which permits legacy IEEE 1149.1 ports to communicate as an IEEE 1149.7 2-wire OScan1 cJTAG port. A simple update to a 1149.1 port to support 1149.7 2-wire signaling. This can be used for reduction in pin count for chips with JTAG interfaces. The IP is in the form of synthesizable verilog. May be implemented in ASIC or FPGA.

Key features

  • IEEE 1149.1 and IEEE 1147.7 compatible.
  • Small logic overhead.
  • Clock frequencies to 25MHz.
  • Activated with a 12b Online Activation Code.
  • Available setup support code for Digilent SDK and OpenOCD.
  • Available CPLD for test system debug prior to silicon.
  • Delivered as obfuscated verilog.

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
OT4001
Vendor
Obsidian Technology
Type
Silicon IP

Provider

Obsidian Technology
HQ: USA
About Obsidian Technology
  • Founded 1995
  • Privately owned consulting company
  • Diversified customer base
  • Self funded
About Obsidian IP
  • Early delivery of front-end models.
  • On-site support available, including transfer of source to your design environment.
  • Available on-site design review.
  • On-site training for source licensing.
  • Option to take ip though your own quality and review processes.
  • Characterization support.
  • Fast and flexible legal. We typically accept your standard bi-directional NDA.
  • Simple plain-language contracts.

Learn more about Test / Debug IP core

Metric Driven Validation, Verification and Test of Embedded Software

Today’s complexity of embedded systems is steadily increasing. The growing number of components in a system and the increased communication and synchronization of all components requires reliable verification, validation and testing of each component as well as the system as a whole. Considering today’s cost sensitivity it is important to find errors as early as possible and to increase the degree of test automation to avoid quality losses because of the increased cost pressure.

eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity

In an era defined by rapid technological advancement, embedded interfaces must evolve to meet the demands of smaller form factors, lower power budgets, and diversified use cases. Among these interfaces, eUSB2V2 (Embedded USB 2.0 Version 2) has emerged not just as a legacy-support PHY, but as a strategic enabler of robust, low-power connectivity across next-generation systems-on-chip (SoCs).

PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions

Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.

Arasan’s xSPI/eMMC5.1 PHY: Unified Dual-Mode Physical Layer IP

As SoCs evolve to support a growing range of memory interfaces, designers are faced with the challenge of balancing integration complexity, pin efficiency, and performance scalability. Traditionally, implementing both xSPI (JESD251) for boot and eMMC 5.1 for high-speed storage required separate PHYs, leading to increased silicon area, power consumption, and I/O overhead.

Frequently asked questions about SerDes Test / Debug IP cores

What is JTAG 2-Wire to 4-Wire Adapter?

JTAG 2-Wire to 4-Wire Adapter is a Test / Debug IP core from Obsidian Technology listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP