Overview
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable core that can be used to evaluate and monitor Virtex-6 GTH transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the serial transceivers. Communication logic is also included, to allow the design to be run-time accessible through JTAG. The IBERT core is a self-contained design, and when it is generated, will run through the entire implementation flow, including bitstream generation.
Learn more about Test / Debug IP core
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