32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. It can work in Generator only, Checker/Counter only or both simultaneously. In error checking mode unit may output PRBS signal, always error free. Embedded 10-bit error counter is accurate: no double counts or omissions regardless of error sequence or frequency of occurrences. Error count may start, stop or be reset at any time with no need to stop or reset the entire unit. Error count range is expandable (see Application Note). Indicator signal facilitates switching between Generator and Checker mode. Footprint is small, no inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only. Unit is designed in TSMC 28HPC/HPC+ process. Design may be ported to more advanced process nodes.

• PRBS order: 31 based on formula: X1=X28^X31
• Full bit rate at input and output up to 32Gbps
• Generator, Checker and Counter functions
• Accurate error count: no omissions or double counts
• Full rate CMOS differential input data, centered with half-rate CMOS differential clock
• Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
• Asynchronous low frequency CMOS control interface
• Supply voltage: 0.9V
• Typical power consumption: 70mA at 32Gbps in simultaneous Generator and Checker mode; scales with bit rate
• Power down mode
• Error counter ready indicator signal
• Operational temperature range: -40C to +110C
• Footprint: 65 x 70 um
• Process: TSMC 28nm HPC/HPC+, portable to more advanced processes

• Unit is intended for testing of communication channels and clock/data recovery systems. Helps to verify functionality and evaluate channel and system quality and efficiency by measuring bit error rates. Unit fits well with Design for Test (DFT) approach and makes an irreplaceable element of advanced Built-in Self Test (BIST) systems.