Vendor: Xilinx, Inc. Category: Test / Debug

IBERT for UltraScale GTH Transceivers

The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale architecture GTH transceivers is desi…

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Overview

The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale architecture GTH transceivers is designed for evaluating and monitoring the GTH transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTH transceivers. Communication logic is also included to allow the design to be run time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration.

Key features

  • Provides a communication path between the Vivado™ serial I/O analyzer feature and the IBERT core
  • Provides a user-selectable number of UltraScale architecture GTH transceivers
  • Transceivers can be customized for the desired line rate, reference clock rate, and reference clock source
  • Requires a system clock that can be sourced from a pin or one of the enabled GTH transceivers

Specifications

Identity

Part Number
IBERT for UltraScale GTH Transceivers
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA
Contact Xilinx, Inc.

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Frequently asked questions about SerDes Test / Debug IP cores

What is IBERT for UltraScale GTH Transceivers?

IBERT for UltraScale GTH Transceivers is a Test / Debug IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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