Vendor: Kamaten Technology Incorporated Category: Test / Debug

32Gbps Pseudo Random Bit Sequence Generator/Checker

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps.

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TSMC 28nm View all specifications

Overview

This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. It can work in Generator only, Checker/Counter only or both simultaneously. In error checking mode unit may output PRBS signal, always error free. Embedded 10-bit error counter is accurate: no double counts or omissions regardless of error sequence or frequency of occurrences. Error count may start, stop or be reset at any time with no need to stop or reset the entire unit. Error count range is expandable (see Application Note). Indicator signal facilitates switching between Generator and Checker mode. Footprint is small, no inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only. Unit is designed in TSMC 28HPC/HPC+ process. Design may be ported to more advanced process nodes.

Key features

  • PRBS order: 7 or 15 based on formulas:   X1=X6^X7; X1=X14^X15. 
  • Full bit rate at input and output is up to 32Gbps. 
  • Generator and Checker functions; will output error free PRBS while in error checking mode. 
  • Accurate error count: no omissions or double counts. 
  • Full rate CMOS differential input data, centered with half-rate CMOS differential clock. 
  • Full rate CMOS differential output data, aligned with half-rate CMOS differential clock. 
  • Accurate embedded 10-bit error counter, externally expandable (see AN for details). 
  • Low frequency asynchronous CMOS control interface. 
  • Supply voltage: 0.9V. 
  • Power down mode. 
  • Typical power consumption: 70mA at 32Gbps in simultaneous Generator and Checker mode; scales with bit rate. 
  • Indicator signal facilitating switching between Generator and Checker mode. 
  • Operational temperature range: -40C to +110C. 
  • Footprint: 65 x 70 um. 
  • Process: TSMC 28nm HPC/HPC+, portable to more advanced processes. 

Applications

  • Unit is intended for testing of communication channels and clock/data recovery systems. Helps to verify functionality and evaluate channel and system quality and efficiency by measuring bit error rates. Unit fits well with Design for Test (DFT) approach and makes an irreplaceable element of advanced Built-in Self Test (BIST) systems.

What’s Included?

  • Technical Brief - TB
  • Data Sheet - DS
  • Application Note - AN
  • Models: Verilog-AMS, Spectre (CC extracted), Spectre (back-annotated)
  • Demo Testbenches - DTB (OA schematics)
  • GDSII Black Box
  • GDSII

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm —

Specifications

Identity

Part Number
PRBS715HS-T28HPC
Vendor
Kamaten Technology Incorporated
Type
Silicon IP

Provider

Kamaten Technology Incorporated
HQ: Canada
Primarily analog and mixed signal IP development for telecommunication, automotive, consumer. Secondary activity: design services provider, full custom analog and mixed signal.
Contact Kamaten Technology Incorporated

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Frequently asked questions about SerDes Test / Debug IP cores

What is 32Gbps Pseudo Random Bit Sequence Generator/Checker?

32Gbps Pseudo Random Bit Sequence Generator/Checker is a Test / Debug IP core from Kamaten Technology Incorporated listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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