Vendor: Cadence Design Systems, Inc. Category: USB

Simulation VIP for USB4

Used by all top market leaders semiconductor companies.The Cadence® Verification IP (VIP) for USB4 provides a capable verificatio…

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Overview

Used by all top market leaders semiconductor companies.

The Cadence<sub>®</sub> Verification IP (VIP) for USB4 provides a highly capable verification solution for the USB4 protocol incorporating bus functional model (BFM) and integrated protocol checkers and coverage. It is based on the next-generation USB protocol architecture of USB4 specification. The VIP for USB4 enables multiple simultaneous data and display protocols and supports them to share the bandwidth over the bus. It supports two-lane operation and up to 40Gbps speed in USB4 Version 1.0 and up to 80Gbps in USB4 Version 2.0.

The VIP for USB4 is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported Specifications: USB4 Specification Version 2.0 and 1.0, and USB4 Re-Timer Specification Version 1.0.

Key features

  • Logical Layer
    • Sideband channel
    • Logical Layer State Machine
    • GEN2, GEN3, and GEN4 speeds
    • Lane initialization and link training
    • Reed-Solomon forward error-correction code (RS-FEC)
    • Dual-lane skew
    • PAM3 encoding and decoding
    • Low-power states
    • Sleep and wake
    • Asymmetric link entry and exit
    • Error cases and recovery
    • Interoperability with Thunderbolt 3 (TBT3) for Logical Layer
  • Transport Layer
    • Transport layer packets
    • Routing
    • Quality of service (QOS): Flow control schemes, bandwidth arbitration and priority
    • Path setup and path tear-down
  • Configuration Layer
    • Router states
    • Control packet protocol
    • Router enumeration
    • Hot plug and hot unplug events
  • Time Synchronization
    • Intra-domain and inter-domain time sync
    • Bi-directional and uni-directional state machines
    • Inversed bi-directional and adaptive uni-directional modes
    • Serial time link protocol
  • Configuration Spaces
    • Support to read and write the defined configuration space for router, adapter, and path
    • Support to backdoor access the configuration space
  • USB3 Tunneling
    • USB3 Gen X and Gen T adapters
    • USB3 adapter layer encapsulation
    • Path setup and tear-down
    • Isochronous Timestamp Mechanism
  • DP Tunneling
    • LTTPR and non-LTTPR mode
    • DP-IN and DP-OUT adapters
    • DP adapter states
    • System flows
    • AUX request and response handling
    • Intra-hop aux
    • Set config, link training for 8b/10b and 128b/132b
    • DP link clock sync
    • 8b/10b SST tunneling
    • 8b/10b MST tunneling
    • 128b/132b tunneling
    • DP FEC
    • HDCP
    • DP panel replay tunneling optimization for 8b/10b and 128b/132b tunneling
  • PCIe® Tunneling
    • PCIe adapter layer encapsulation
    • Any max packet size
    • Extended encapsulation
    • Path setup and tear-down
    • Precision time management (PTM) mechanism
  • Re-Timer
    • Sideband channel
    • Re-timer channel state machine
    • Low power
    • Clock switching
    • Interoperability with Thunderbolt 3 (TBT3) compatibility

Block Diagram

Simulation VIP for USB4 block diagram

Files

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Specifications

Identity

Part Number
Simulation VIP for USB4
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about USB IP cores

What is Simulation VIP for USB4?

Simulation VIP for USB4 is a USB IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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