How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
RLDRAM2 Synthesizable Transactor
RLDRAM2 Synthesizable Transactor provides a smart way to verify the RLDRAM2 component of a SOC or a ASIC in Emulator or FPGA plat…
Overview
RLDRAM2 Synthesizable Transactor provides a smart way to verify the RLDRAM2 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's RLDRAM2 Synthesizable Transactor is fully compliant with standard RLDRAM2 Specification and provides the following features.
Key features
- Supports 100% of RLDRAM2 protocol standard
- Supports all the RLDRAM2 commands as per the specs
- Supports the following devices:
- X9
- X18
- X36
- Supports 8 internal banks for concurrent operation and maximum bandwidth
- Supports reduce cycle time (15ns at 533MHZ)
- Supports non multiplexed addresses (address multiplexing option available)
- Supports SRAM-type interface
- Supports programmable read latency (RL), row cycle time, and burst sequence length
- Supports balanced read and write latencies in order to optimize data bus utilization
- Supports data mask for write commands
- Supports data valid signal (QVLD)
- Supports on-die termination (ODT) RTT
- Supports IEEE 1149.1 compliant JTAG boundary scan
- Supports full-timing as well as behavioral versions in one model
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations
Block Diagram
RLDRAM2 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the RLDRAM2 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
RLDRAM2 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about DDR Controller IP cores
What is RLDRAM2 Synthesizable Transactor?
RLDRAM2 Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.