Vendor: InCirT GmbH Category: PLL

Ring oscillator-based analog PLL

Low energy consumption Our ring oscillator-based analog PLL provides good phase noise performance with extremely low energy consu…

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GlobalFoundries 22nm FDX View all specifications

Overview

Low energy consumption

Our ring oscillator-based analog PLL provides good phase noise performance with extremely low energy consumption and small area compared to the state-of-the-art products. The programmable divider allows to shift the output frequency with a large locking range.

Key features

  • For input reference frequency ranges of 50MHz, 125MHz and 250MHz
  • Different frequency ranges (DLLs available as well)
  • All parameters adjustable upon request
  • Low power consumption
  • Small Area
  • Low jitter
  • Wide frequency range
  • Silicon verified in GF 22FDX

Benefits

  • All parameters adjustable upon request
  • Low power consumption
  • Small Area
  • Low jitter
  • Wide frequency range

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX —

Specifications

Identity

Part Number
PLL
Vendor
InCirT GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

InCirT GmbH
HQ: Germany
InCirT GmbH provides the state-of-the-art high performance, ultra low power data converters, the best figure of merits featured PLL, DLL and high speed interface as well as other mixed-signal blocks. InCirT has multiple tapeout experiences in different technologies and generates highly sophisticated SoCs including both mixed-signal and ASIC designs. The generated IPs provide high cost and energy efficient solutions as well as high integrability. InCirT also provides custom-based design IPs which help customers to develop their optimal solutions for their architecture. With the diverse and highly experienced design teams, InCirT can provide several design services in different areas ranging from custom ASIC design to Silicon IP design and verification. InCirT’s multigigabit BW and extreme low power dataconverters and sub-ps jitter PLLs leading the best figure of merit IC chips.
Contact InCirT GmbH

Learn more about PLL IP core

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Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Ring oscillator-based analog PLL?

Ring oscillator-based analog PLL is a PLL IP core from InCirT GmbH listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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