RAPIDIO EndPoint Controller IIP

RapidIO EP interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect 2.2 specification. Through its RapidIO EP compatibility, it provides a simple interface to a wide range of low-cost devices. RapidIO EP IIP is proven in FPGA environment. The host interface of the RapidIO EP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

RAPIDIO EndPoint Controller IIP is supported natively in Verilog and VHDL

• Compliant with RapidIO Interconnect 2.2 specification
• Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
• Supports high link utilization and low latency
• Supports efficient receive and transmit buffering scheme
• Supports 34-bit addressing
• Supports 8-bit device ID
• Supports programmable source ID on all outgoing packets
• Supports request class transactions: NREAD and ATOMIC set/clr/inc/dec/test and swap for read-modify-write operations
• Supports write class transactions: NWRITE, NWRITE_R
• Supports the Maintenance read request and Maintenance write request transactions
• Supports Doorbell and Data Message class transactions
• Supports streaming write class transactions: SWRITE
• Supports the Continuous packet transactions
• Supports the Parallel packet transactions
• Supports the below physical layer features
• 1x/2x/4x serial lane support with integrated transceivers
• Supports per-lane speeds of 1.25, 2.5, 3.125, 5.0 and 6.25Gbaud
• Receive/Transmit packet buffering and error detection
• Automatic freeing of resources used by acknowledged packets
• Automatic retransmission of retried packets
• Supports interrupt for each error detection and for complete serial message reception
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The RapidIO EP interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.