Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SmartDV Technologies
Category:
SRAM
QDR2 Synthesizable Transactor
QDR2 Synthesizable Transactor provides a smart way to verify the QDR2 component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
QDR2 Synthesizable Transactor provides a smart way to verify the QDR2 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's QDR2 Synthesizable Transactor is fully compliant with standard QDR2 Specification and provides the following features.
Key features
- Supports 100% of QDR2 protocol standard CY7C1314CV18
- Supports separate independent read and write data ports with concurrent read and write operation
- Supports full data coherency, providing most current data
- Supports synchronous pipeline read with self-timed late write
- Supports registered address, control and data input/output
- Supports QDR (quad data rate) interface on read and write ports
- Supports fixed 4-bit burst for both read and write operation
- Supports two input clocks (K and K) for accurate QDR timing at clock rising edges only
- Supports two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches
- Supports two echo clocks (CQ and CQ) to enhance output data traceability
- Supports single address bus
- Supports byte write function
- Supports simple depth expansion with no data contention
- Supports programmable output impedance
- Supports single multiplexed address input bus latches address inputs for both read and write ports
- Supports separate port selects for depth expansion
- Supports synchronous internally self-timed writes
- QDR II operates with 1.5 cycle read latency when delay lock loop (DLL) is enabled
- Operates similar to a QDR I device with one cycle read latency in DLL off mode
- Supports available in x18, and x36 configurations
- Supports variable drive HSTL output buffers
- Supports all the QDR2 commands as per the specs
- Supports delay lock loop (DLL) for accurate data placement
- Supports full-timing as well as behavioral versions in one model
- Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing protocol violations
Block Diagram
QDR2 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the QDR2 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
QDR2 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SRAM IP cores
What is QDR2 Synthesizable Transactor?
QDR2 Synthesizable Transactor is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.