PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
Overview
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device. The TX is designed to send information from PHY to PSRAM and RX is designed to receive information which is from PSRAM. there are bi-direction DQ IO, TX-only CK IO, filler cell with differrent size and VDDQ/VSS power clamp IO included in the PHYIOs.
Key features
- Compatible with JESD251C
- Data Rate: Up to 1066 Mbps
- Support OCD drive strength config and trimming
- 240/200/100/66/50/40/33/25 Ω
- Block cell includes Local Decap and ESD cell
- Process Node: TSMC 22nm
- Operation Temperature: Tj = -40℃ ~ +125℃
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 22nm | ULL | — |
Specifications
Identity
Provider
Learn more about Single-Protocol PHY IP core
Design IP Faster: Introducing the C~ High-Level Language
Universal Flash Storage: Mobilize Your Data
Can MIPI and MDDI Co-Exist?
Enter the Inner Sanctum of RapidIO: Part 1
Networking software key to PICMG 2.16 optimization
Frequently asked questions about Single-Protocol PHY IP
What is PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm?
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm is a Single-Protocol PHY IP core from UniIC listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.