Vendor: Rambus, Inc. Category: PCI Express

PCIe 7.0 Switch with with Time Division Multiplexing

The PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementati…

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PCIe 7.0 View all specifications

Overview

The Rambus PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe with TDM support designed for ASIC and FPGA implementations. It enables the connection of one upstream port and multiple downstream ports as a fully configurable interface subsystem. It is backward compatible to PCIe 6.3 and PCIe 5.0.

How the PCIe 7.0 Switch Works

The PCIe 7.0 Switch is the first embedded PCIe 7.0 switch IP available on the market and enables designers to use fewer PCIe PHYs, saving latency, power consumption and bill-of-material costs. The PCIe switch IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs.

Key features

PCI Express Interfaces

  • Up to 2 upstream port, up to 31 downstream ports
  • Up to 128 lanes
  • Bifurcated port groups – x16 down to x4 with TDM support
  • Up to x16 link width per port
  • Link rate of 2.5, 5, 8, 16, 32, 64 and 128 GT/s per lane
  • Supports PCIe Base Revision 7.0 and 6.3
  • Supports PHY Interface for PCIe (PIPE) 7.0
  • Single Virtual Channel (VC) implementation
  • Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit, 128 bit)
  • Configurable Receive and Replay buffer sizes
  • Advanced Error Reporting (AER) supported on each port
  • ECRC generation and check
  • ARI supported
  • Lane reversal supported
  • Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port
  • Support for Hot Plug on every downstream port

Switching Logic

  • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
  • L1 and wake-up events forwarding
  • Peer-to-Peer transactions support between downstream ports
  • Configurable Egress Buffer for non-blocking output queueing switch performance
  • Broadcast and Multicast supported
  • Downstream Port Containment (DPC) supported
  • Round-Robin arbitration
  • Built-in advanced data protection including ECRC, LCRC, ECC and Parity
  • Test port available for switch logic monitoring
  • Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic
  • Physically aware switch architecture: configurable pipeline stages and fully non-blocking multi-stage routing crossbar
  • Data Bus Inversion support for EM/IR reduction of large busses
  • Manages multiple packet per clock cycle

Block Diagram

PCI Express 7.0 Switch with TDM Block Diagram

What’s Included?

  • Switch Development Platform (equivalent to a reference design) with several configurations available
  • Documentation (User Guide)
  • Technical support and maintenance updates
  • Switch reference design

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
PCIe 7.0 Switch
Vendor
Rambus, Inc.
Type
Silicon IP

Standards & Interfaces

PCIe Version
PCIe 7.0

Provider

Rambus, Inc.
HQ: USA
Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, our products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next-generation computing platforms, we make data faster and safer.
Contact Rambus, Inc.

Learn more about PCI Express IP core

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Frequently asked questions about PCIe IP cores

What is PCIe 7.0 Switch with with Time Division Multiplexing?

PCIe 7.0 Switch with with Time Division Multiplexing is a PCI Express IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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