Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

PHY for PCIe 3.1

The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and aut…

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PCIe Gen3 View all specifications

Overview

The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols. ​

Key features

  • Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
  • Multi-protocol support for simultaneous independent links
  • Supports SRIS and internal SSC generation
  • Supports PCIe L1 sub-states
  • Automatic calibration of on-chip termination resistors
  • Supports internal and external clock sources with clock active detection
  • SCAN, BIST, and serial/parallel loopback functions

Block Diagram

PHY for PCIe 3.1 block diagram

What’s Included?

  • PMA Hard Macro
  • PCS-BIST Soft Macro
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Specifications

Identity

Part Number
PHY for PCIe 3.1
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Standards & Interfaces

Supported Standards
PCIe Gen3

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is PHY for PCIe 3.1?

PHY for PCIe 3.1 is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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