NVMe Verification IP

NVMe Verification IP provides an smart way to verify the NVMe bi-directional bus. The SmartDV's NVMe Verification IP is fully compliant with NVM-Express-1_4-2019.06.10-Ratified specification and provides the following features.

NVMe Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

NVMe Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports NVM-Express-1_4-2019.06.10-Ratified specification.
• Support all Admin commands
• Support all IO commands
• Support for all Transaction types/Opcodes.
• UVM and Verilog APIs supplied, as well as C DPI exports
• Automated Error Injections at all layers
• Checkers verify protocol timing checks and functional accuracy at each layer
• Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
• Supports Interrupt Mechanism
• Supports Data Integrity as End to End Data Protection
• Supports Submission and completion queue management
• Supports Controller Memory Buffer
• Supports memory description as PRP/SGL description list
• Supports Boot partitions operations
• Supports additional data insertion by Metadata
• Supports doorbell buffer configurations
• Supports error reporting and recovery mechanism
• Supports reservation feature
• Supports directive feature
• Supports Namespace subsystem
• NVMe over PCIe
• - > Supports complaint and optimized TLP packets.
• - > Supports PIPE, PCS/PMA, and serdes interface
• - > Full link speed and width negotiation up to 32 Lanes
• - > Queuing for VCs with configurable depth
• - > Configurable TC to VC queue mapping
• - > User interface for direct TLP queuing and receipt
• - > Checks all TLPs for correct formation of headers, prefixes, and ECRC
• - > Full DL state machines
• - > Checks all framing, LCRC, and lane rules
• - > Check all DLLP fields and formatting
• - > Interface to send / receive user defined DLLPs
• - > Full LTSSM state machine
• - > SERDES model with digital clock recovery
• - > Supports Up configure, polarity inversion, and lane-to-lane skew
• - > Configurable Spread Spectrum Clocking (SSC)
• - > Configurable timers and timeouts
• - > Supports for Conventional PCI Advanced Features
• - > Supports PAM4 encoding scheme
• - > Supports Gray coding and Tx Precoding
• - > Supports Flit mode and non flit mode
• - > Supports Forward Error Correction mechanism
• - > Supports L0p state
• - > Supports Shared Credit Pool
• - > Supports Link management DLLP
• - > Compliant with PIPE 5.2.1 Specification
• NVMe Verification IP comes with complete test suite to test every feature of NVMe specification.
• Supports UNH-IOL testing service
• Functional coverage for complete NVMe features.
• Callbacks in BFM’s and Monitor for various events.

• Faster testbench development and more complete verification of NVMe designs.
• Easy to use command interface simplifies testbench control and configuration of NVMe Host and Controller.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the NVMe testcases to certify NVMe BFM's.
• Examples showing how to connect various components, and usage of NVMe BFM and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.