LPDDR5 Synthesizable Transactor
LPDDR5 Synthesizable Transactor provides a smart way to verify the LPDDR5 component of a SOC or a ASIC in Emulator or FPGA platfo…
Overview
LPDDR5 Synthesizable Transactor provides a smart way to verify the LPDDR5 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR5 Synthesizable Transactor is fully compliant with standard LPDDR5 Specification and provides the following features.
Key features
- Supports 100% of LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B.
- Supports all the LPDDR5 commands as per the specs
- Supports device density up to 32GB
- Supports X8 and X16 device modes
- Supports 2:1 and 4:1 CKR mode
- Supports all data rates as per specification
- Supports burst length 16 and 32
- Supports programmable read/write latencies
- Supports following back organization modes
- Bank group (4 Bank 4 Bank group)
- 8 Bank
- 16 Bank
- Supports burst sequence
- Supports all mode register programming
- Supports write DBI and read DBI operation
- Supports write data mask operation
- Supports WCK2CK Sync operation
- Supports deep sleep mode
- Supports power down mode and self-refresh operation
- Supports frequency set point operation
- Supports Refresh Management Command.
- Supports following training modes
- Command bus training
- WCK2CK leveling
- WCK-DQ training
- Enhanced RDQS training mode
- Supports partial array self refresh segment masking
- Supports write clock free running mode
- Supports data copy low power function and write x operation
- Supports hybrid refresh mode and refresh credit mode
- Supports CA parity and ECC
- Checks for following
- Check-points include power on, Initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc
- All timing violations
- Protocol checker fully compliant with LPDDR5 Specification JESD209-5, JESD209-5A and JESD209-5B
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the LPDDR5 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about LPDDR IP
What is LPDDR5 Synthesizable Transactor?
LPDDR5 Synthesizable Transactor is a LPDDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this LPDDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.