LPDDR4x/4 PHY IP for 22nm

OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solution or independent IP. They are tightly combined to bring synergy for high performance and low latency. OPENEDGES' integrated IP solutions are market and silicon-proven, featuring advanced architectures and proprietary technologies that enable customers to shorten their design and verification processes.

The LPDDR4x/4 OPHY features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables OPHYs to overcome issues with long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without interruption of data traffic. The programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between OMC and the LPDDR4 DRAM without sacrificing performance.

The LPDDR4x/4 OPHY was designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage.
At the system level, the LPDDR4x/4 OPHY was desinged to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications and application processors.

• Compliant for JEDEC standards for LPDDR4x/4 with PHY standards
• DFI Interface Compliant
• Supports 1,2, or 4 ranks
• Multiple frequency states
• PHY independent training and calibration
  • Firmware based training
  • Hardware or Firmware based retraining
  • Proprietary microcontroller with custom ISA
• Multiple DFICLK: CK ratios
• Tx and Rx channel equalization
• Voltage and temperature tracking of timing and impedance control circuit
• Flexible floor planning/bump mapping

• Configurability with Flexible Applications
• Cost effective with minimal package substrate/PCB layer requirments
• High Performance
  • Fimware-based training / ultra-fast fractional training
  • Fast switching between FSPs
  • Programmable PHY boundary timing providing low read/write latency
• Maximize capacity with channel equalization at multi rank
• Low Power scheme using power-saving mode and multiple voltage domains

• Consumer edge devices
• Digital set-top-boxes
• TVs
• SSD controllers
• Application processors

• Hard & Soft IP
  • GDSII, LEF, LVS, timing models, etc.
  • Verilog behavior models and encrypted RTL
  • Synthesis and STA constraints
  • Example test benches
• Documentation
  • PHY Technical Reference Manual
  • Implementation, package, and PCB design guidelines
  • Test and characterization guidelines
  • Physical verification reports