LPDDR PHY

LPDDR5X, LPDDR5, LPDDR4X, LPDDR4, LPDDR3 PHY and Controller

The PHY and Controller for LPDDR5X/5/4X/4/3 is a family of high-speed on-chip memory interface IP that satisfy high-performance requirements with products that are optimized for each application's needs.

The latest LPDDR5X/5 PHY and Controller IP support the newest Low-Power Double Data Rate 5 (LPDDR5) JEDEC standard with data rates of up to 8533Mbps. The LPDDR5X/5 IP product line is a new high-speed architecture that is based on Cadence’s industry-leading LPDDR5 6400Mbps and GDDR6 22Gbps products. The architecture targets high-performance products that require low power and post-silicon programmability. The high-performance design features dynamic feedback equalization (DFE), feed foreword equalization (FFE), and continuous time linear equalization (CTLE), as well as per-bit read and write delay adjustment. Cadence’s proprietary ultra-low jitter clock trees and DLLs, proven in the GDDR6 22Gbps product line, contribute to better system timing margins, lower cost package and PCB designs, and overall system reliability. Multiple low-power modes and configurations are supported and target industry-leading exit latencies, multiple frequency set points (FSP) in hardware, and dynamic frequency scaling (DFS).

The LPDDR5X/5 IP products are designed to integrate easily into most applications. The PHY IP can be delivered as either firm or hard macros, supporting multiple floorplan and bump map options. The PHY top-level logic uses low clock frequencies to enable easier, faster, and more reliable timing closure.

The LPDDR Controller delivers a wide array of capabilities to address emerging LPDDR DRAM subsystem RAS, ECC, parity, and data-scrubbing functions. The application-optimized LPDDR5 PHY and Controller can achieve industry-leading data rates, with low-power features that include multiple low-power states for longer battery life and greener operation.

• Application-optimized configurations for fast time to delivery and lower risk
• Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
• I/O pads with impedance calibration logic and data-retention capability
• Fine-grain custom delay cell for delay tuning
• Internal and external datapath loop-back modes
• RX and TX equalization for heavily loaded systems
• Programmable per-bit (PVT compensated) deskew on read and write datapaths

• Communications,
• Consumer Electronics,
• Data Processing,
• Industrial and Medical,
• Military/Civil Aerospace

• Verilog post-layout netlist
• STA scripts for use at chip or standalone PHY levels
• Liberty timing model
• SDF for back-annotated timing verification
• Verilog models of I/O pads, and RTL for all PHY modules