LPDDR2 Synthesizable Transactor
LPDDR2 Synthesizable Transactor provides a smart way to verify the LPDDR2 component of a SOC or a ASIC in Emulator or FPGA platfo…
Overview
LPDDR2 Synthesizable Transactor provides a smart way to verify the LPDDR2 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR2 Synthesizable Transactor is fully compliant with standard JESD209-2E and JESD209-2F Specification and provides the following features.
Key features
- Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F
- Supports all the LPDDR2 commands as per the specs
- Supports up to 32GB device density
- Supports following devices:
- X8
- X16
- X32
- Supports all speed grades as per specification
- Supports programmable write latency and read latency
- Supports programmable burst lengths: 4, 8 and 16
- Supports following burst types:
- Sequential
- Interleave
- Checks for following:
- Check-points include power up,initialization and power off rules
- State based rules, active command rules
- Read/write command rules etc
- All timing violations
- Supports all mode registers/control programming
- Supports NVM device
- Supports ZQ calibration
- Supports DQ calibration
- Supports overlay window enable/disable
- Supports write data mask
- Supports power down features
- Supports deep power down features
- Supports auto precharge option for each burst access
- Supports full-timing as well as behavioral versions in one model
- Optional partial array self refresh and temperature compensated self refresh
- Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the LPDDR2 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about LPDDR IP
What is LPDDR2 Synthesizable Transactor?
LPDDR2 Synthesizable Transactor is a LPDDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this LPDDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.