Vendor: SmartDV Technologies Category: LPDDR

LPDDR Synthesizable Transactor

LPDDR Synthesizable Transactor provides a smart way to verify the LPDDR component of a SOC or a ASIC in Emulator or FPGA platform.

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Overview

LPDDR Synthesizable Transactor provides a smart way to verify the LPDDR component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR Synthesizable Transactor is fully compliant with standard JESD209B and JESD209A-1 Specification and provides the following features.

Key features

  • Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1
  • Supports all the LPDDR commands as per the specs
  • Supports up to 2GB device density
  • Supports following devices:
    • X16
    • X32
  • Supports all speed grades as per specification
  • Supports programmable CAS latency
  • Supports programmable burst lengths: 2,4,8 and 16
  • Checks for following:
    • Check-points include power up,initialization and power off rules
    • State based rules, active command rules
    • Read/write command rules etc
    • All timing violations
  • Supports all mode registers/control programming
  • Supports extended mode registers programming
  • Supports the following burst types:
    • Sequential
    • Interleave
  • Supports burst order
  • Supports write data mask
  • Supports power down features
  • Supports deep power down features
  • Supports auto precharge option for each burst access
  • Supports auto refresh and self refresh modes
  • Supports full-timing as well as behavioral versions in one model
  • Optional partial array self refresh and temperature compensated self refresh
  • Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

LPDDR Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the LPDDR testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
LPDDR Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about LPDDR IP

What is LPDDR Synthesizable Transactor?

LPDDR Synthesizable Transactor is a LPDDR IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this LPDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this LPDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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