Low-Offset Programmable Gain Amplifier on UMC 55nm
This present IP is applied to amplify the input signal with the programmable gain in Standalone/PGA mode or to work as a buffer i…
Overview
This present IP is applied to amplify the input signal with the programmable gain in Standalone/PGA mode or to work as a buffer in Follower mode, which operates in 1.8v~3.6v power supply and 1.2v power supply for control signals.
Key features
- Low input offset
- rail-to-rail input/output voltage range
- Support 3 working mode with the programmable gain
- Supply voltage: VDD33: 1.8v~3.6v, VDD12: 1.2v±10%.
- Process: UMC 55nm Logic and Mixed-mode Low Leakage Process
- Operation Temperature: Tj = -40℃ ~ +105℃
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 55nm | 55nm 550 nm | — |
Specifications
Identity
Provider
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Frequently asked questions about Amplifier IP cores
What is Low-Offset Programmable Gain Amplifier on UMC 55nm?
Low-Offset Programmable Gain Amplifier on UMC 55nm is a Amplifier IP core from UniIC listed on Semi IP Hub. It is listed with support for umc.
How should engineers evaluate this Amplifier?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Amplifier IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.