JTAG Verification IP
The JTAG Verification IP provides an effective & efficient way to verify the components interfacing with the JTAG interface of an…
Overview
The JTAG Verification IP provides an effective & efficient way to verify the components interfacing with the JTAG interface of an ASIC/FPGA or SoC.
The JTAG VIP is fully compliant with Standard JTAG Version IEEE 1149.1-2013 JTAG specification from JEDEC. This VIP is lightweight with an easy plug-and-play interface so that there is no hit on the design time and the simulation time.
Key features
- Supports IEEE 1149.1-2013 JTAG Protocol Standard.
- DUT can be:
- Master
- Slave
- Configurable instruction register.
- Configurable data register width.
- Dynamically configurable data register width.
- User-defined instructions.
- User-defined data registers.
- Reports current state of TAP finite state machine.
- Support for both public and private instructions.
- User-defined BFM instructions.
- Support for all Test Access Port (TAP) pins.
- Internal and external clock and reset modes.
- Supports constraints randomization.
- Status counters for various events on the bus.
- Supports callbacks for a user to define a custom instruction decoder.
- Supports callbacks for a user to get a callback on each state of the TAPcontroller.
- Support all types of timing and protocol violation detection.
- Functional coverage for checking all possible stimulus checking.
- Protocol-aware debug.
Benefits
- Available in native SystemVerilog(UVM/OVM/VMM) and Verilog
- Unique development methodology to ensure the highest level of quality.
- Availability of Compliance & Regression TestSuites.
- 24X5 customer support
- Unique and customizable licensing models
- Exhaustive set of assertions and cover pointswith connectivity example for all thecomponents.
- Consistency of interface, installation,operation, and documentation across all over.
What’s Included?
- JTAG Driver BFM/Agent
- JTAG Monitor & Scoreboard
- JTAG Controller BFM/Agent
- Test-Bench Configurations
- Test Suite (Available in Source code)
- Basic Protocol Tests
- Directed & Random Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual, and Release Notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
- To create world class Verification IP Solutions
- To provide expert consultancy to ASIC & SoC Design companies
- To design SOCs from Architecture to Working Silicon
- To be the leading provider of Semiconductor IP Solutions
- To be a one-stop-shop for Design and Verification
- Customer Success
- Commitment to Quality
- Quality of Products
- Quality of Engineers
- Best in class Customer Support
- Ethics and Integrity
Learn more about Test / Debug IP core
Metric Driven Validation, Verification and Test of Embedded Software
Tools for Test and Debug : Embedded designers face a myriad of multiprocessor challenges
eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Arasan’s xSPI/eMMC5.1 PHY: Unified Dual-Mode Physical Layer IP
Frequently asked questions about SerDes Test / Debug IP cores
What is JTAG Verification IP?
JTAG Verification IP is a Test / Debug IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this Test / Debug?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.