Vendor: SmartDV Technologies Category: Test / Debug

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor provides a smart way to verify the JTAG component of a SOC or a ASIC in Emulat…

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Overview

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor provides a smart way to verify the JTAG component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor is fully compliant with standard JTAG Specification and provides the following features.

Key features

  • Follows JTAG basic specification as defined in JTAG Specification 3
  • Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
  • Supports all the JTAG tap instructions
  • Supports programmable clock frequency of operation
  • Supports checks for following
    • Check-points include Initialization rules
    • State based rules,Active Command rules
    • Read/Write to Instruction and data register Rules
  • Supports instruction register and data register of size up to 64 bits
  • Supports proficiency to extend with user defined instructions and registers
  • Has ability to read BSDL file and
    • Automatically generate testvectors to test all BSDL cell types
    • Automatically generate SVA assertions properties
  • Supports all types of timing and protocol violation detection

Block Diagram

JTAG (IEEE 1149.1/1149.6) Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the JTAG (IEEE 1149.1/1149.6) testcases
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JTAG (IEEE 1149.1/1149.6) Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SerDes Test / Debug IP cores

What is JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor?

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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