Vendor: SmartDV Technologies Category: Test / Debug

Xccela Flash Memory Model

Xccela Flash Memory Model provides an smart way to verify the Xccela Flash component of a SOC or a ASIC.

Contact Provider Request Datasheet

Overview

Xccela Flash Memory Model provides an smart way to verify the Xccela Flash component of a SOC or a ASIC. The SmartDV's Xccela Flash memory model is fully compliant with standard Xccela Flash Specification and provides the following features. Better than Denali Memory Models.

Xccela Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Xccela Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports Xccela Flash memory devices like MT35X_QLJW_U_256_ABA/ MT35X_QLKA_L_01G_BBA/ MT35X_QLKA_U_02G_CBA from all leading vendors
  • Supports 100% of Xccela Flash protocol Standards.
  • Supports all the Xccela Flash commands as per the specs.
  • Supports Single and double transfer rate (SDR/DDR)
  • Supports following protocols
    • Octal DDR protocol
    • Extended-SPI protocol with octal commands
  • Supports Execute-in-place (XIP).
  • Supports volatile and nonvolatile configuration settings.
  • Supports software reset.
  • Supports 3-byte and 4-byte addressing modes
  • Supports 64-byte OTP area outside main memory.
    • Readable and user-lockable
    • Permanent lock with Program OTP commands
  • Supports Program/Erase/Suspend operation.
  • Supports the following Erase capability
    • Bulk erase
    • Sector erase 128KB uniform granularity
    • Subsector erase 4KB, 32KB granularity
  • Supports security and write protection
    • Volatile and nonvolatile locking and software write protection
    • Nonvolatile configuration locking
    • Password protection
    • Hardware write protection
    • CRC
  • Supports all types of timing and protocol violation detection.
  • Constantly monitors Xccela Flash behavior during simulation.
  • Protocol checker fully compliant with Xccela Flash Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

Xccela Flash Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of Xccela Flash designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the Xccela Flash testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Xccela Flash Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about Test / Debug IP core

Metric Driven Validation, Verification and Test of Embedded Software

Today’s complexity of embedded systems is steadily increasing. The growing number of components in a system and the increased communication and synchronization of all components requires reliable verification, validation and testing of each component as well as the system as a whole. Considering today’s cost sensitivity it is important to find errors as early as possible and to increase the degree of test automation to avoid quality losses because of the increased cost pressure.

eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity

In an era defined by rapid technological advancement, embedded interfaces must evolve to meet the demands of smaller form factors, lower power budgets, and diversified use cases. Among these interfaces, eUSB2V2 (Embedded USB 2.0 Version 2) has emerged not just as a legacy-support PHY, but as a strategic enabler of robust, low-power connectivity across next-generation systems-on-chip (SoCs).

PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions

Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.

Arasan’s xSPI/eMMC5.1 PHY: Unified Dual-Mode Physical Layer IP

As SoCs evolve to support a growing range of memory interfaces, designers are faced with the challenge of balancing integration complexity, pin efficiency, and performance scalability. Traditionally, implementing both xSPI (JESD251) for boot and eMMC 5.1 for high-speed storage required separate PHYs, leading to increased silicon area, power consumption, and I/O overhead.

Frequently asked questions about SerDes Test / Debug IP cores

What is Xccela Flash Memory Model?

Xccela Flash Memory Model is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP