Provider
Dolphin Technology
HQ:
USA
Dolphin Technology provides SoC designers with a broad array of silicon-proven IP for Memory, I/O, Standard Cells, DDR PHY, Memory Controllers, PLL/DLL and Memory Test and Repair (BIST).
Dolphin offers both standard and custom solutions that are optimized for low power, high performance and high density across a broad range of process technologies. These solutions include:
- Memory Compilers (Single & Dual Port SRAM, 1 & 2 Port RF, ROM)
- Specialty Memory (ROM, BCAM, TCAM, CAM)
- I/O (General purpose, bus-specific, DDR, Flash)
- Standard Cell libraries (7-track, 10-track, 12-track, 14-track)
- DDR PHY (hardened DDRx & LPDDRx SDRAM PHY)
- PLL/DLL (programmable PLL, fully digital DLL)
- SERDES
- Memory Controllers (DDRx & LPDDRx DRAM)
- Memory BIST
- And more...
Dolphin Technology has been enabling SoC design teams to enhance quality and reduce time to market since 1996.
Learn more about Test / Debug IP core
How to use advanced logging techniques to fill in a critical gap in the debug and analysis of SystemVerilog testbench code and replace the manual gathering and analysis of text log files
Today’s complexity of embedded systems is steadily increasing. The growing number of components in a system and the increased communication and synchronization of all components requires reliable verification, validation and testing of each component as well as the system as a whole. Considering today’s cost sensitivity it is important to find errors as early as possible and to increase the degree of test automation to avoid quality losses because of the increased cost pressure.
Tools for Test and Debug : Embedded designers face a myriad of multiprocessor challenges
In an era defined by rapid technological advancement, embedded interfaces must evolve to meet the demands of smaller form factors, lower power budgets, and diversified use cases. Among these interfaces, eUSB2V2 (Embedded USB 2.0 Version 2) has emerged not just as a legacy-support PHY, but as a strategic enabler of robust, low-power connectivity across next-generation systems-on-chip (SoCs).
Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.
As SoCs evolve to support a growing range of memory interfaces, designers are faced with the challenge of balancing integration complexity, pin efficiency, and performance scalability. Traditionally, implementing both xSPI (JESD251) for boot and eMMC 5.1 for high-speed storage required separate PHYs, leading to increased silicon area, power consumption, and I/O overhead.