Vendor: SmartDV Technologies Category: JESD204

JESD204 Synthesizable Transactor

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces.

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Overview

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces. JESD204 is build on top of it to make it robust. JESD204 Synthesizable Transactor provides a smart way to verify the JESD204 component of a SOC or a ASIC in Emulator or FPGA platform.JESD204 Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Follows JESD204 specification JESD204A, JESD204B and JESD204C
  • Supports Transmitter and Receiver Mode
  • Supports up to 32 lanes
  • Supports 32bit data width per converter
  • Supports up to 32 converters per transmitter & receiver BFM
  • Scrambler can be enabled or disabled
  • Supports 8b/10b link layer functions
  • Supports 64b/66b link layer functions based on IEE802.3 Clause 49 and JESD204C
  • Supports 64b/80b link layer functions with fill bit encoding based on IEEE802.3 clause 49 and JESD204C
  • Supports Forward Error Correction (FEC), cyclic redundancy checks (CRC) and command channel
  • Supports single block, Multi block and extended multi block
  • Provides error injection and error detection with a wide variety of error types. Which includes:
    • Invalid code group insertion
    • Disparity errors
    • CRC errors
    • Sync error insertion
    • Lane skew insertion
    • FEC errors
    • Scrambler error insertion

Block Diagram

JESD204 Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the JESD204 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD204 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204 Synthesizable Transactor?

JESD204 Synthesizable Transactor is a JESD204 IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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