Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor …
Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor for short, transaction-related transfers. A look-aside coprocessor is connected "to the side" of the datapath, and is not in-line of the main datapath of the switch, router, or other networking device. Interlaken Look-Aside is not directly compatible with Interlaken and can be considered a different operational mode.
Interlaken Look-Aside Interconnect Protocol
The Interlaken Look-Aside IP core is suited for coprocessing packet classification typically used for networking applications such as: Quality of service routing, traffic profiling, and firewall functions. The IP's low-latency packet interface, coupled with its efficient data processing capability, enables a high degree of design scalability for emerging network applications.
This IP core includes Intel's technology-leading transceivers:
The PCS and PMA layers are hardened within the Stratix® 10, Arria® 10, Stratix V, and Arria V FPGAs.
Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate with new protocol features to provide customers with robust and easy-to-implement Interlaken Look-Aside IP solutions. The Interlaken Look-Aside Intel FPGA IP core offers a wide range of bandwidths up to 300G.
The Interlaken Look-Aside IP core is Interlaken Look-Aside Protocol Definition v1.1 compliant and allows system developers to eliminate the computational bottlenecks associated with older, packet classification methods. Intel also offers customized Interlaken Look-Aside IP solutions. For more information, please contact your local sales representative.
Intel and Cavium Team Up to Provide Pre-verified Packet Classification Solution
The Interlaken Look-Aside Intel FPGA IP core on a Stratix® V FPGA with Cavium’s NEURON Search Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.
To further simplify our customers’ decision-making process, Intel and Cavium have generated an interoperability report that details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset. Contact your sales person for a copy of this report.
Intel and Cavium Connectivity System Overview
The Interlaken Look-Aside Intel FPGA IP core on a Stratix® V FPGA with Cavium’s NEURON Search Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.
To further simplify our customers’ decision-making process, Intel and Cavium have generated an interoperability report that details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset. Contact your sales person for a copy of this report.
Note: some files may require an NDA depending on provider policy.
Interlaken Look-Aside Intel® FPGA IP is a Interlaken IP core from Altera listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Interlaken IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.