8530 Multi-Protocol Controller
8530 MPSC Controller (Multi-Protocol Serial Communication Controller) is a general-purpose communication controller which consist…
- HDLC
- Not Applicable
- Available
- FPGA IP Core
HDLC IP cores enable standards-based low-speed control and peripheral communication in modern SoC and ASIC designs.
These IP cores support framed serial communication with bit-oriented data link control for telecom, industrial, and infrastructure systems, helping designers integrate interoperable control links across embedded, automotive, industrial, and connectivity-focused systems
This catalog allows you to compare HDLC IP cores from leading vendors based on feature set, latency, power consumption, and process node compatibility.
Whether you are designing networking equipment, industrial communications, control systems, or legacy infrastructure, you can find the right HDLC IP for your application.
8530 Multi-Protocol Controller
8530 MPSC Controller (Multi-Protocol Serial Communication Controller) is a general-purpose communication controller which consist…
Used for controlling HDLC/SDLC transmission protocols
The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol.
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390.
High-Level Data Link Controller
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Tra…
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent tr…
Full-featured asyn/hdlc serial channel
HDLC & SDLC Protocol Controller
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC…
The Dual HDLC controller provides two full-duplex HDLC channels, each with 512-byte data FIFO buffers for both directions.
Aliathon’s HDLC Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for HDLC inte…