Vendor: V-Trans Microelectronics Category: Single-Protocol PHY

FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)

Now available up to 150Mhz (90Mhz previously) V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI speci…

Contact Provider Request Datasheet

Overview

Now available up to 150Mhz (90Mhz previously)

V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the transfer of digital display data between a display source and a display device.
This receiver converts 5 LVDS, (low voltage differential signaling) data streams, into 30bits (single pixel) CMOS data plus 5 control signals (VSYNC, HSYNC, DE, and 2 user-defined signals).
At a maximum pixel rate of 90Mhz, LVDS data line speed is 630Mbps, providing a total maximum bandwidth of 3.15Gb/s (394Mbytes per second).


Key features

  • 1P6M layout structure based on 0.18um 1P6M 1.8V generic logic process.
  • 3.3V/1.8V 10% supply voltage, 0/+125C
  • Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
  • Up to 3.15Gbps bandwidth (8 to 90Mhz pixel clock for 1 channel)
  • Parallel output clock edge is programmable
  • Spread-spectrum input clock support
  • Compact core cell area : [contact us]
  • Built-in power pads with ESD protection.
  • Low leakage power-down mode <0.1uA.
  • Equivalent part : Thine’s THC63LVD104A

Benefits

  • Very compact design
  • customization for your own project
  • reliability

What’s Included?

  • Design kit includes :
    • LEF view and abstract gdsII
    • Verilog HDL behavioral model
    • Liberty (.lib) timing constraints for typical, worse and best corner case
    • Full Datasheet /Application Note with integration guidelines document
    • Silicon characterization report when available

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
VT18LVD104
Vendor
V-Trans Microelectronics

Provider

V-Trans Microelectronics
HQ: CHINA
V-Trans provides a low cost solution with high performance mixed-signal IPs which are very easy to integrate into your SOC. Together, our US Silicon-Valley experience and local talents, combined with a cost effective operation in Shanghai, China, we provide you a full support and customization through tapeout.
Contact V-Trans Microelectronics

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)?

FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA) is a Single-Protocol PHY IP core from V-Trans Microelectronics listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP