GCRAM, the highest-density on-chip embedded memory in standard CMOS
RAAAM’s Gain-Cell RAM (GCRAM) is the most cost-effective on-chip memory technology in the semiconductor industry.
- TSMC
- 16nm
Memory IP cores are fundamental building blocks in modern SoC and ASIC designs, enabling efficient data storage and memory access.
These IP cores include embedded memories such as SRAM, ROM, Flash, and EEPROM, as well as memory controllers for external memory interfaces like DDR and LPDDR.
This catalog allows you to explore and compare memory IP cores from leading vendors based on performance, density, power consumption, and process node compatibility.
Whether you are designing high-performance computing systems, low-power IoT devices, or automotive applications, you can find the right memory IP for your system requirements.
GCRAM, the highest-density on-chip embedded memory in standard CMOS
RAAAM’s Gain-Cell RAM (GCRAM) is the most cost-effective on-chip memory technology in the semiconductor industry.
RAM 8b, 16b, and 32b data widths - TSMC 180nm
Low cost, small RAM’s in standard design rules supplied in 1Kb, 4Kb, and 16Kb fixed block sizes.
Ultra High-Speed Cache Memory Compiler - 2-Port Register File - TSMC N3P
The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an cache …
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…
NVM MTP in TSMC (180nm, 152nm, 65nm, 55nm, 40nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…
NVM FTP Trim in TSMC (180nm, 152nm, 150nm, 130nm)
Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in stand…
High Speed Single Port Compiler on TSMC 40nm ULP
Single port SRAM compiler with low power retention mode Bit Cell Power Supply (V) 6T 1.1 Process Technology TSMC 40nm ULP Supply …
64x1 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V General Purpose Process
The ATO00064X1TS180SGE3NA is organized as a 64-bit by 1 one-time programmable (OTP).
16x8 Bits OTP (One-Time Programmable) IP, TSMC CM018G 0.18um 1.8V/3.3V Process
The ATO00016X8TS180CMG3NA is organized as 16 bits by 8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.
4Kx8 Bits OTP (One-Time Programmable) IP, TSMC 0.18µm 1.8V/5V Mixed-Signal Process
The ATO0004KX8TS180MSS3NA is organized as a 4Kx8 one-time programmable in parallel mode.
32x8 Bits OTP (One-Time Programmable) IP, TSMC 0.18um Mixed-Signal 1.8V/3.3V Process
The ATO00032X8TS180GS33NA is organized as 32x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.
768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V Process
The ATO0768X39TS055ULP4NL is organized as 768x39 one-time programmable (OTP).
4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process
The ATO4608X12TS040ULP7ZA is organized as 4608 x 12 one-time programmable (OTP).
1Kx8 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
The ATO0001KX8TS040ULP5ZA is organized as 1 kb x 8 one-time programmable (OTP).
High-Density eMRAM Compiler TSMC 22ULL
The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…
256x16 Bits OTP (One-Time Programmable) IP, TSMC 152nm 1.8V/3.3V GP MS Process
The AT256X16T152LP0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes.
The ATO00128X8TS055ULP3NA is organized as 128x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.
1x32 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP).
768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V Process
The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP).
16Kx33 Bits OTP (One-Time Programmable) IP, TSMC 40LP 1.1V/2.5V Process
The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP).