Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SmartDV Technologies
Category:
SRAM
FCRAM Synthesizable Transactor
FCRAM Synthesizable Transactor provides a smart way to verify the FCRAM component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
FCRAM Synthesizable Transactor provides a smart way to verify the FCRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's FCRAM Synthesizable Transactor is fully compliant with standard FCRAM Specification and provides the following features.
Key features
- Supports 100% of FCRAM protocol standard FCRAM specifications
- Supports all the FCRAM commands as per the specs
- Supports up to 512MB device density
- Supports up to four internal banks
- Supports programmable write latency
- Supports programmable burst lengths:
- 2
- 4
- 8
- 16
- Supports sequential burst type
- Supports burst order
- Supports all mode registers programming
- Checks for following:
- Check-points include power on, initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports self refresh, power down and deep power down operation
- Supports auto refresh operation
- Supports additional RDQS toggle (ART)
- Supports write data mask and data strobe features
- Supports background refresh and burst terminate operations
- Supports clock stop capability during idle periods
- Supports both synchronous and asynchronous on-die termination modes
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
FCRAM Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the FCRAM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
FCRAM Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about SRAM IP cores
What is FCRAM Synthesizable Transactor?
FCRAM Synthesizable Transactor is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.