Master/Slave DLL

The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing. This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint.

The DLL PHY is designed to generate precise phase-shifted clocks (e.g. 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission. It consists of the Master DLL and Slave DLL, each serving specific roles in the clock distribution network.

• Reference clock frequency range from 200MHz to 800MHz
• Generates accurate phase-shifted clocks (e.g., 0/90/180/270) synchronized with the reference clock
• Optimized for low-power operation
• Ensures proper alignment for high-speed data sampling and transmission
• Provides stable and reliable clock alignment
• Allows customization of delay settings, phase shifts and other parameters to meet specific application requirements
• Designed to mitigate the effects of noise and jitter
• Cycle to Cycle jitter (C2C): ≤150ps

• Low power consumption
• Fully customizable
• High speed hub using VLPI low latency
• Small area
• Simple integration process

• GDSII
• LVS Spice netlist
• Verilog model
• Synopsys synthesis model
• LEF for clock generator PLL
• User Guidelines