800Mb/s DDR DLL on TSMC CLN55LP
Digital ICs that interface to high speed consumer memory interfaces such as mobile DDR receive data and strobe clocks simultaneou…
Overview
Digital ICs that interface to high speed consumer memory interfaces such as mobile DDR receive data and strobe clocks simultaneously. In order to ensure timing and guarantee data-capture, the incoming clocks need to be phase adjusted, typically by 90 degrees. In addition, the strobe clocks appear non- continuously as a method of reducing switching power and hence will require a clock system generation macro to rapidly generate clocks.
Analog Bits DLL macro generates a 90 degree delayed clocks from non-continuous clock strobe. The macro also has a built-in stop capability that allows powering down the analog portions when the incoming clock is idling saving power. Additionally the macro has the ability to perform rapid re-start the clocks with the incoming clocks. The macro is also provided with programmable gate-delays which can be used to compensate for external data-path or clock-tree delays.
Electrical Properties Parameter Units Min Typ Max Comment Reference Frequency MHz 100 400 Frequency of REF, STROBE may be slower.
DDR Performance Mbps 200 800 Reference Duty Cycle % 40 60 Strobe Duty Cycle % 40 60 Duty Cycle Degradation % -2% +2% Lock Time Cycles 512 Cycles of input reference clock from RESET Lock Time Cycles 0 Cycles of input reference clock from coasting Static Phase Error ps -50 +50 DLLOUT rising edge phase error at 325MHz Cycle to Cycle Jitter ps -50 +50 With constant reference frequency and analog grade power supply Operational Voltage V 1.08 1.2 1.32 Operational Temperature C -40 25 125 Table 1: DLL Operational Range
Key features
- Generates precise degrees of clock phase shifting for mobile or standard DDR applications
- Phase adjustments of non-continuous strobe clocks
- Compensates for external clock and data delays
- Programmable delay for precise and granular control of delay
- Quick stop/re-start capability for power management
- Uses Analog Bits proprietary architecture that uses core logic devices only
- Uses no external on-chip components or band-gaps minimizing power consumption
- Excellent jitter performance with optimized noise correction
- Multiple output options and other configurations available upon request
- Angular control options available upon request
- Higher speed options available upon request
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 55nm | LP | — |
Specifications
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Frequently asked questions about DLL IP cores
What is 800Mb/s DDR DLL on TSMC CLN55LP?
800Mb/s DDR DLL on TSMC CLN55LP is a DLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this DLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.