Deep Buffering Memory 1G Ethernet Switch

Advanced switch supporting buffering of large amounts of data in external DDR RAM

The 1G deep buffering memory Ethernet Switch is an advanced Ethernet switching IP that supports buffering large amounts of data in external RAM. The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization, enabling per port and per queue shaping on egress ports.

The 1G deep buffering memory Ethernet switch IP from Comcores supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency. Each port provides a native interface for GMII Ethernet PHY devices.

Delivers Performance

• QoS features like classification, queuing, and priorities included
• Automatic MAC address learning and aging
• Supports buffering of up to 128 MB in DDR
• Extensive statistic reporting

Highly Configurable

• Buffer size is fully configurable
• Configurable scheduling (round-robin, strict priority, among others)
• Configurable tagging

Easy to Use

• Solid Verification Environment
• Easy integration on Xilinx evaluation platforms
• GMII interfaces for attaching external Physical Layer devices (PHY)

Silicon Agnostic

• Designed in Verilog and targeting both ASICs and FPGAs

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual and Release Note
• Simulation Environment, including Simple Testbed, Test case and Test Script
• Programming Register Specification
• Timing Constraints in Synopsys SDC format
• Access to support system and direct support from Comcores Engineers
• Synopsys SGDC Files (optional)
• Synopsys Lint, CDC and Waivers (optional)