Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm

The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-mo…

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GlobalFoundries 12nm LP Silicon Proven View all specifications

Overview

The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications. Our PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.

Key features

  • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
  • Autonomous initialization
  • Support for x72 bit channel
  • Support for multiple DRAM widths (x4, x8, x16, x32)
  • Support for single channel, 1 to 4 ranks
  • Selectable low-power operating states
  • DFI 3.1 compliant for easy integration with memory controller
  • Programmable output impedance and on-die termination
  • ZQ calibration of output impedance and on-die calibration
  • Utilizes standard 8-layer 6020 metal layer stack

What’s Included?

  • Fully-Characterized hard macro (GDSII)
  • Complete design views
  • Full documentation and datasheet

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP Silicon Proven

Specifications

Identity

Part Number
DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
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Frequently asked questions about Single-Protocol PHY IP

What is DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm?

DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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