How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR3 Monitor Verification IP
DDR3 Monitor provides an smart way to verify the DDR3 component of a SOC or a ASIC.
Overview
DDR3 Monitor provides an smart way to verify the DDR3 component of a SOC or a ASIC. The SmartDV's DDR3 Monitor is fully compliant with standard DDR3 Specification and provides the following features.
DDR3 Monitor Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR3 Monitor Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports DDR3 memory devices from all leading vendors
- Quickly validates the implementation of the DDR3 standard
- Constantly monitors DDR3 behavior during simulation
- Checks for following
- Check-points include Initialization rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- Support for full-timing as well as behavioral versions in one model
- Support for all timing delay ranges in one model: min, typical and max
- Built in coverage analysis
- Supports Callbacks, so that user can access the data observed by monitor.
Block Diagram
DDR3 Monitor VIP block diagram
Benefits
- Faster testbench development and more complete verification of DDR3 designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the DDR3 testcases.
- Examples showing how to connect and usage of Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
DDR3 Monitor VIP
Vendor
SmartDV Technologies
Provider
SmartDV Technologies
HQ:
India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Learn more about DDR IP core
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Frequently asked questions about DDR Controller IP cores
What is DDR3 Monitor Verification IP?
DDR3 Monitor Verification IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.