DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package

The DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMS. The highly configurable controller meets or exceeds the design requirements of a wide range of applications from data center to consumer. The DDR5/4 Controller connects to the DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution. The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.

The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.

The DDR Controller seamlessly integrates the Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. The Secure DDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the secure memory controllers is as low as 2 clock cycles.

• Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
• Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
• DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
• Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
• High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
• UVM testbench with embedded assertions and options to incorporate a DDR5/4 PHY into a verification environment
• Secure Controller: Integrated IME Security Module for data confidentiality