How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Synopsys, Inc.
Category:
DDR
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)
Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…
Overview
Synopsys offers a complete system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5X/5, LPDDR4/4X, LPDDR3, LPDDR2, HBM3, HBM2E and HBM2 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the silicon-proven Synopsys DDR Memory Interface IP products include a choice of scalable digital controllers with Inline Memory Encryption (IME) Security Module, an integrated hard macro or configurable PHY delivering memory system performance of up to 8.5Gbps, and verification IP.
Synopsys' DDR and LPDDR PHYs are supportd by Synopsys' unique Synopsys DDR PHY Compiler for determining the area and power of a customer-specific configuration.
Synopsys DDR5/4, LPDDR5X/5/4/4X Controllers, and Enhanced Universal DDR Memory and Protocol Controller IP feature a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA CHI, AXI/4 AXI Quality of Service (QoS) and advanced Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs. The Synopsys Inline Memory Encryption (IME) Security Module seamlessly integrates with Synopsys DDR and LPDDR controllers to provide confidentiality and data protection.
Key features
- Four memory controller offerings: uMCTL2: multi-ported memory controller supporting JEDEC standard DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, and LPDDR4, and LPDDR4X SDRAM and DIMM modules
- uPCTL2: Single-ported version of uMCTL2 with no internal scheduler; DDR5/4 controller: multi-ported memory controller supporting JEDEC standard DDR5, DDR4 SDRAMs and DIMM modules
- LPDDR5/4/4X controller: multi-ported memory controller supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- High-bandwidth design with up to 64 CAM entries for Reads and 64 CAM entries for Writes, and latency as low as 6 clock cycles
- Best in class performance with unique features such as QoS based scheduling and dual-channel support
- Offers several RAS features, such as Sideband ECC, Inline ECC, Command/Address Parity, etc., where supported by the DRAM protocol
- In-line ECC function provides error correction in systems that cannot use a sideband ECC
- LPDDR5/4/4X controller and uMCTL2 have an automotive license option, which has been designed with automotive safety features and includes ISO 26262 Work Products
Benefits
- #1 supplier of DDR interface IP (IPnest 2017)
- Comprehensive DDR IP solution includes protocol and memory controllers and PHY IP
- Products support various combinations of DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, and LPDDR standards
- Each solution supports at least two generations of DDR standards (for example, DDR5 and DDR4)
Specifications
Identity
Part Number
dwc_ddr_lpddr_2_3_4_5_controller
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
Synopsys, Inc.
HQ:
USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS)?
DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) is a DDR IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.