How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Cadence Design Systems, Inc.
Category:
DDR
Denali High-Speed DDR PHY for SMIC
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area Devel…
Overview
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area
Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the DDR PHY IP is silicon proven and can provide customers with ease of integration and faster time to market. The DDR PHY IP is engineered to quickly and easily integrate into any system on chip (SoC), and is verified with the Denali DDR controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller. The DDR PHY IP is developed and validated to reduce the risk for the customer so that their SoC can be first-time right. Developed for and available early in the lifecycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips. The DDR PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of an interface, Denali memory interface, analog, and systems and peripherals IP.
Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the DDR PHY IP is silicon proven and can provide customers with ease of integration and faster time to market. The DDR PHY IP is engineered to quickly and easily integrate into any system on chip (SoC), and is verified with the Denali DDR controller IP as part of a complete memory subsystem solution. The DDR PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller. The DDR PHY IP is developed and validated to reduce the risk for the customer so that their SoC can be first-time right. Developed for and available early in the lifecycle of the most advanced semiconductor process nodes, the DDR PHY IP is designed to be robust under varying noise conditions and to have interoperability with various supplier memory chips. The DDR PHY IP is part of the comprehensive Cadence Design IP portfolio comprised of an interface, Denali memory interface, analog, and systems and peripherals IP.
Key features
- LPDDR4X/LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
- Optional clock gating available for low-power control
- Memory controller interface complies with DFI standards 4.0 or 3.1
- Internal and external datapath loopback modes
- I/O pads with impedance calibration logic and data retention capability
- Multiple PLLs for maximum system margin
- Programmable clock delay (PVT compensated) on read and write datapaths for DQS alignment
- Per-bit deskew on read and write datapath
Applications
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace
What’s Included?
- GDS II macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Liberty timing model
- SDF for back-annotated timing verification
Specifications
Identity
Part Number
Denali High-Speed DDR PHY for SMIC
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster.
The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR IP Hardening - Overview & Advance Tips
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is Denali High-Speed DDR PHY for SMIC?
Denali High-Speed DDR PHY for SMIC is a DDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.