How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Cadence Design Systems, Inc.
Category:
DDR
DDR5/4 PHY for TSMC 16nm
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area The l…
Overview
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area
The latest, the DDR5/4 PHY IP for TSMC 16nm, is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized DDR PHY IP can achieve speeds up to 4800Mbps. Low-power features include the addition of VDD low-power idle state in the PHY, and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce overall area by up to 20%. The PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Cadence Denali Controller IP for DDR as part of a complete memory subsystem solution. The PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller.
The latest, the DDR5/4 PHY IP for TSMC 16nm, is comprised of architectural improvements to its highly successful predecessor, achieving breakthrough performance, lower power consumption, and smaller overall area. The applicationoptimized DDR PHY IP can achieve speeds up to 4800Mbps. Low-power features include the addition of VDD low-power idle state in the PHY, and power-efficient clocking during low-speed operation for longer battery life and greener operation. Redesigned I/O elements reduce overall area by up to 20%. The PHY IP is developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Cadence Denali Controller IP for DDR as part of a complete memory subsystem solution. The PHY IP is designed to connect seamlessly and work with a thirdparty DFI-compliant memory controller.
Key features
- Application optimized configurations for fast time to delivery and lower risk
- Memory controller interface complies with DFI standards up to 5.0
- Internal and external datapath loop-back modes
- Per-bit deskew on read and write datapath
- Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
- I/O pads with impedance calibration logic and data retention capability
- RX and TX equalization for heavily loaded systems
- Fine-grain custom delay cell for delay tuning
Applications
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace
What’s Included?
- GDSII macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Liberty timing model
- SDF for back-annotated timing verification
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 16nm | 16nm 160 nm | Available on request |
Specifications
Identity
Part Number
DDR5/4 PHY for TSMC 16nm
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Files
Note: some files may require an NDA depending on provider policy.
Provider
Cadence Design Systems, Inc.
HQ:
USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.
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The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements.
Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Learn more about DDR IP core
The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Secure DDR DRAM Against Rowhammer, RAMBleed, and Cold-Boot Attacks
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
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DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
Which DDR SDRAM Memory to Use and When
This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.
DDR5/4/3/2: How Memory Density and Speed Increased with each Generation of DDR
Frequently asked questions about DDR Interface IP
What is DDR5/4 PHY for TSMC 16nm?
DDR5/4 PHY for TSMC 16nm is a DDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.