Vendor: True Circuits, Inc. Category: PLL

TSMC CLN40FLOD 40nm IoT PLL - 30MHz-750MHz

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power.

TSMC 40nm FLOD View all specifications

Overview

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to 250MHz. It is ideal for IoT applications like wearables and senor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.

Key features

  • Optimized for very low power, running completely from core power supply.
  • Supports 32KHz reference clocks.
  • Extremely wide range of operation with multiplication factors over 8,000.
  • Small area, delivered as a single hard macro with guardrings and isolation.
  • Flexible and highly programmable.
  • Ideal for low power and cost sensitive applications such as IoT wearables and remote sensors.

What’s Included?

  • GDSII (100% DRC and LVS clean)- LVS Spice netlist- Verilog model- Synopsys synthesis model- LEF for clock generator PLL- User Guidelines including:
  • integration guidelines,
  • layout guidelines,
  • testability guidelines,
  • packaging guidelines,
  • board-level guidelines

Silicon Options

Foundry Node Process Maturity
TSMC 40nm FLOD

Specifications

Identity

Part Number
TCI-TN40FLOD-ITHPLL
Vendor
True Circuits, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

True Circuits, Inc.
HQ: USA
True Circuits develops and markets a broad range of industry leading PLL, DLL and DDR PHY hard and soft macros for ICs for the semiconductor, systems and electronics industries. TCI’s robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world’s leading fabs, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. The True Circuits DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is managed by a light weight special purpose processor for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings. True Circuits DDR PHYs support LPDDR5, DDR4, LPDDR4, DDR3 and LPDDR3 in single and multi-protocol versions and are available in a wide variety of TSMC processes. They are configured to each customer’s die floorplan and package constraints, and are delivered and verified as a single unit for easy timing closure with no assembly required. They are DFI 5.1 compliant, and when combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized. True Circuits’ complete family of standardized and silicon-proven clock generator, general purpose, deskew, spread spectrum, IoT and Ultra PLLs and multi-slave and multi-phase DLLs spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low jitter PLL and DLL hard macros are optimized for a wide variety of interface standards, including DDR, HBM, ONFI, PCIE, Ethernet and HDMI. True Circuits also offers synthesizable PLLs and DLLs with timing features, performance and flexibility for a wide range of customer applications. These soft macros include the Precision PLL, micro PLL and micro DLL. True Circuits PLLs and DLLs are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in a wide variety of TSMC, UMC and GlobalFoundries processes. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks. Since 1998, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers’ products with production volumes well into the billions. When only the best will do, go with the timing experts!

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

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Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is TSMC CLN40FLOD 40nm IoT PLL - 30MHz-750MHz?

TSMC CLN40FLOD 40nm IoT PLL - 30MHz-750MHz is a PLL IP core from True Circuits, Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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