SMPTE Decoder with Colour-Space Converter

The HD_SMPTE_DECODER IP Core  is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a standard SMPTE video stream and convert them to 24-bit RGB pixels for subsequent processing.

Video decoding begins after reset is de-asserted and on the rising-edge of clk. Output RGB pixels are generated on each active line starting with the first frame.

The 4:2:2 Pixels are extracted from the SMPTE input stream and converted to RGB888 format. These pixels are then presented at the output of the decoder together with the sync flags. The pixout_val signal is active high for the duration of each active line and it is disabled during blanking periods.

If necessary, the output of the decoder may be stalled by asserting pixout_rdy low. While pixout_rdy is low then pixels will be buffered in an internal FIFO. If pixout_rdy is low for greater than a full line of video then the FIFO will fill to capacity and the overflow flag will be asserted. All signals are synchronous with the rising-edge of the pixel clock.

• Technology independent soft IP Core for FPGA, ASIC and SoC
• Supplied as human-readable VHDL (or Verilog) source code
• Fully pipelined architecture with AXI4-stream (compatibility)
• Converts industry standard 20-bit 4:2:2 SMTPE digital video to 24-bit RGB pixels + sync flags
• Integrated 4:2:2 YCbCr to RGB888 colour-space converter
• All HD720p and HD1080p (progressive) video formats supported including SMPTE 296M and SMPTE 274M
• All signals synchronous with the pixel clock
• Small implementation size ideal for all types of FPGA
• Compatible with a wide range of video decoder ICs

• Conversion of progressive SMPTE video formats
• Connectivity with a wide range of commercially available video decoder ICs, 3G-SDI, HD-SDI and HDMI receivers
• Simple and cost-effective method for capturing digital video into your FPGA, ASIC or SoC