Vendor: VeriSyno Microelectronics Co., Ltd. Category: Single-Protocol PHY

USB 2.0 PHY

The USB 2.0 PHY is a mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to…

Contact Provider Request Datasheet
USB 2.0 View all specifications

Overview

The USB 2.0 PHY is a complete mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to a specific fabrication process using core and 2.5-V thick-oxide devices. The USB 2.0PHY supports the USB 2.0 480-Mbps protocol and data rate and is backward compatible with the USB 1.1 1.5-Mbps and 12-Mbps protocol and data rates.

Key features

  • ? 480-Mbps high-speed, 12-Mbps full-speed, and 1.5-Mbps low-speed serial (Host mode only) data transmission rates
  • ? Supports high-speed power modes: suspend, resume, and remote wakeup.
  • ? USB 2.0 test modes
  • ? 45-? termination, 1.5-k? pull-up and 15-k? pull-down resistors with support for independent control of the pull-down resistors
  • ? 8/16-bit unidirectional parallel interfaces for HS, FS, and LS (Host mode only) modes of operation in accordance with the UTMI+ specification
  • ? Dual (HS/FS) mode host/device support (LS operation is not supported for device applications)
  • ? Data recovery from serial data on the USB connector
  • ? SYNC/End-of-Packet (EOP) generation and checking
  • ? Bit stuffing and unstuffing, and bit-stuffing error detection
  • ? Non Return to Zero Invert (NRZI) encoding and decoding
  • ? Bit serialization and deserialization
  • ? Holding registers for staging transmit and receive data
  • ? Logic to support suspend, resume, and remote wakeup operations
  • ? VBUS threshold comparators
  • ? Parameter override bits for optimal yield and interoperability
  • ? Fully integrated short-to-5-V and short-to-ground protection for D+ and D– lines (requires only global ESD and 5-V-compliant DP/DM pads)

What’s Included?

  • We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Specifications

Identity

Part Number
USB 2.0 PHY
Vendor
VeriSyno Microelectronics Co., Ltd.
Type
Silicon IP

Standards & Interfaces

Supported Standards
USB 2.0

Provider

VeriSyno Microelectronics Co., Ltd.
HQ: The People's Republic of China
VeriSyno Microelectronics Co., Ltd. is a national high-tech enterprise dedicated to the research and development of semiconductor IPs. The company’s main products include mixed-signal high-speed interface IPs such as USB, HDMI, DDR, MIPI, PCIe, SATA, and various analog IPs such as ADC, DAC, PLL, LVDS, as well as independently developed PSRAM interface IO solutions and vMAC series IPs. As one of the important semiconductor IP suppliers in China, in active collaboration with local foundries, VeriSyno has long been committed to the porting of those mature interface IPs to processes such as 22/28/40/55nm, to ensure secure and reliable supply of domestic IPs. The company’s diversified IP products have been widely used in industries such as industrial, medical, AI, and IoT. VeriSyno was established in September 2018 and is headquartered in Hefei, Anhui, with branch offices in Beijing, Shanghai, and Shenzhen.
Contact VeriSyno Microelectronics Co., Ltd.

Learn more about Single-Protocol PHY IP core

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Design IP Faster: Introducing the C~ High-Level Language

In this paper, we introduce a new high-level, dataflow programming language called C~ (“C flow”) that further increases productivity by raising the level of abstraction from behavioral descriptions, while overcoming the limitations of C for hardware design. We present the syntax and semantics of this language, and the framework that provides hardware and software code generation. This paper illustrates the benefits of using C~ for hardware design of a IEEE 802.3 MAC, synthesized for FPGA and for 90nm CMOS technology.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Can MIPI and MDDI Co-Exist?

Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?

Frequently asked questions about Single-Protocol PHY IP

What is USB 2.0 PHY?

USB 2.0 PHY is a Single-Protocol PHY IP core from VeriSyno Microelectronics Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP