Vendor: VeriSyno Microelectronics Co., Ltd. Category: Single-Protocol PHY

PCIe Gen1 PHY

The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…

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Overview

The PCIe1 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into computer applications. The PCIe1 PHY pcie1_pipe_1xN includes all the necessary logical, geometric, and physical design files to implement complete PCI Express 1.1 physical layer capability for 2.5-Gbps operation, connecting a host or device controller to a PCI Express system.

Key features

  • ? 2.5-Gbps data transmission rate
  • ? Supports 16-bit interface at 250-MHz operation
  • ? Supports 32-bit interface at 125-MHz operation
  • ? Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
  • ? Programmable Rx equalization
  • ? Supports collapsing of power supplies
  • ? Supports x1/x2/x4 configurations
  • ? Supports low power mode
  • ? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply
  • ? Excellent performance margin and receiver sensitivity
  • ? Robust PHY architecture that tolerates wide process, voltage, and temperature variations
  • ? Low-jitter PLL technology with excellent supply isolation
  • ? IEEE 1149.6 (JTAG) boundary scan
  • ? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester
  • ? Supports 2.5-Gbps PCIe Gen 1.1 test mode
  • ? Advanced, built-in diagnostics including on-chip sampling scope for easy debug
  • ? Visibility and controllability of hard macro functions through programmable registers in the design
  • ? Overrides on all ASIC side inputs for easy debug
  • ? Access register space through simple 16-bit parallel interface
  • ? Access register space through JTAG port

What’s Included?

  • We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Specifications

Identity

Part Number
PCIe Gen1 PHY
Vendor
VeriSyno Microelectronics Co., Ltd.
Type
Silicon IP

Provider

VeriSyno Microelectronics Co., Ltd.
HQ: The People's Republic of China
VeriSyno Microelectronics Co., Ltd. is a national high-tech enterprise dedicated to the research and development of semiconductor IPs. The company’s main products include mixed-signal high-speed interface IPs such as USB, HDMI, DDR, MIPI, PCIe, SATA, and various analog IPs such as ADC, DAC, PLL, LVDS, as well as independently developed PSRAM interface IO solutions and vMAC series IPs. As one of the important semiconductor IP suppliers in China, in active collaboration with local foundries, VeriSyno has long been committed to the porting of those mature interface IPs to processes such as 22/28/40/55nm, to ensure secure and reliable supply of domestic IPs. The company’s diversified IP products have been widely used in industries such as industrial, medical, AI, and IoT. VeriSyno was established in September 2018 and is headquartered in Hefei, Anhui, with branch offices in Beijing, Shanghai, and Shenzhen.
Contact VeriSyno Microelectronics Co., Ltd.

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Frequently asked questions about Single-Protocol PHY IP

What is PCIe Gen1 PHY?

PCIe Gen1 PHY is a Single-Protocol PHY IP core from VeriSyno Microelectronics Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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