High-Definition SMPTE Test Pattern Generator

The HD_SMPTE_TPG IP Core is a versatile test pattern generator capable of producing a range of test patterns in 20-bit 4:2:2 format. The output stream format is compliant with the SMPTE standards 296M and 274M. The module is ideal for use in the prototyping stages of digital video systems or as a known good reference source for standard 720p, 1080p or 1080i video.

The video mode is controlled by the generic parameter hd_mode and the video test pattern can be set using the parameter tpg_type. In total there are 8 different test patterns to choose from.

The output video is a standard SMPTE 20-bit stream that is synchronous with the clk signal. The clock frequency should be set to the value that corresponds to the correct pixel clock frequency for the corresponding video mode. For instance, the clock frequency should be set to 74.25 MHz for 720p60, 1080p30 or 1080i60 modes. A clock frequency of 148.5 MHz should be chosen for 1080p60.

• Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
• Supplied as human-readable VHDL (or Verilog) source code
• Test patterns generated as an industry standard 20-bit 4:2:2 SMPTE stream
• YCbCr 4:2:2 output pixels
• All 720p, 1080p and 1080i video formats supported (SMPTE 296M and SMPTE 274M)
• Colour-bar output with choice off 8 different patterns
• All signals synchronous with the pixel clock
• Compatible with a wide range of video encoder ICs
• Tiny implementation size makes the core suitable for even the smallest FPGAs and CPLDs

• Digital video testing and prototyping
• Default output displays and simple 'screen savers'