Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain

PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32. The serializer (except 32 bit outputs) is implemented based on differential CML logic for robust operation under strong noise coupling through power, ground and substrate. The data signal is applied to a 50Ω terminated data input is equalized to restore the data eye by the bandwidth limited media such as transmission lines on FR-4 PCBs or coaxial cable. The selectable equalizer can be tuned for the best performance with particular media. An automatic offset control with overriding option (manual or FEC directed) is built in for correcting of duty cycle distorted data such as in fiber optic receivers. The limiting amplifier following the equalizer is conditioning the data eye for robust CDR operation. CDR phase as well as its dynamics can be adjusted to meet specific jitter tolerance and jitter transfer specifications. Line rate data (8.5-11.3Gb/s) is deserialized to 32-bit parallel data stream and converted to CMOS format for feeding into a FEC or other digital processing block or for feeding out (LVDS output buffers are necessary). Multiple dividers (including fractional N) are implemented for support of different clocking modes: 79:85, 85:79 (FEC+G.709) 14:15, 15:14 (FEC only) 237:239, 239:237 (G.709 only) 255:239, 239:255 (add FEC to G709 frame) when macro is integrated with a complimentary serializer. All biasing currents are programmable within +/-30% for operational margin estimation in production. LOL and LOS with programmable thresholds are built in for loss of lock and loss of signal indication. DC test points are integrated for measurement of internal temperature, bias voltages and ground potential. I/Os are integrated for loop back to serializer macro for link testing purposes. Layout is designed using IBM CMOS10LPE 5_01_00_01_LD metal stack. Control functions and layout configuration can be customized upon special agreement.